【AndTech】 December 17th (Tuesday) AndTech “Latest trends in
nanoimprint lithography mechanism and semiconductor microfabrication, application to metaverse (AR/VR)” WEB online Zoom seminar scheduled to be held
AndTech Press release: November 13, 2024 December 17th (Tuesday) AndTech “Mechanism of nanoimprint lithography and semiconductor microfabrication, latest trends towards application to metaverse (AR/VR)” WEB online Zoom seminar scheduled to be held We will have lectures from Mr. Yoshihiko Hirai from Osaka Public University, Mr. Yuji Komatsu from Connectec Japan Co., Ltd., and Mr. Tomohiro Iwaki from Micron Memory Japan Co., Ltd. (Micron Technology, Inc.). Image
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semiconductor and metaverse applications, which have been increasing recently, as part of a Zoom course for R&D development support. To this end, we will be offering a course on “Nanoimprint Lithography – Semiconductor/Metaverse Applications” led by leading instructors. Introducing the latest trends in the application of nanoimprint lithography microfabrication technology to semiconductors and metaverse (AR/VR)! This course is scheduled to start on December 17,
2024. Details: https://andtech.co.jp/seminars/1ef97433-b6d1-6cce-882a-064fb9a95405 Live distribution/WEB seminar course overview ────────────────── Theme: Mechanism of nanoimprint lithography, semiconductor
microfabrication, and latest trends toward application to metaverse (AR/VR) Date and time: Tuesday, December 17, 2024 13:00-17:05 Participation fee: 49,500 yen (tax included) * Materials will be distributed electronically U R L ：
https://andtech.co.jp/seminars/1ef97433-b6d1-6cce-882a-064fb9a95405 Web distribution format: Zoom (URL will be sent after application) Seminar course content composition ──────────── -Program/Instructor- ∽∽────────────────────────∽∽ Part 1 Nanoimprint application to optical waveguides for AR/VR (overview and application to tilted diffraction gratings) ∽∽────────────────────────∽∽ Lecturer: Professor Emeritus, Osaka Prefecture University / Specially Selected Researcher, Osaka Public University / Advisor, Nanoimprint Technology Research Group, Japan Society of Applied Physics / Director, 3D Heterointegration Research Group (3DHI), Mr. Yoshihiko Hirai
∽∽────────────────────────∽∽ Part 2 Application of imprint technology to semiconductor packaging ∽∽────────────────────────∽∽ Lecturer: Mr. Yuji Komatsu, General Manager, Advanced Development Department, Connectec Japan Co., Ltd. ∽∽────────────────────────∽∽ Part 3 Development of nanoimprint lithography technology and application to semiconductor microfabrication ∽∽────────────────────────∽∽ Lecturer: Micron Technology, Inc. MTS – PHOTO DRAM Tomohiro Iwaki Knowledge that can be learned and technical issues that can be solved in this seminar ──────────────────────── ・Nanoimprint application to optical waveguide for AR/VR ・Low temperature flip chip bonding process and its application examples ・Semiconductor chip packaging integration trends ・Application of imprint technology to semiconductor packaging Format of this seminar ────────────── This will be a live streaming seminar using the web conferencing tool “Zoom”. Details will be provided after you apply. About AndTech Co., Ltd. ────────────
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https://prcdn.freetls.fastly.net/release_image/80053/963/80053-963-ca3cbd4e93bc1c9dd45006d9ac2cd477-1920×1005.jpg We will dispatch a highly specialized technical consultant with a wealth of experience. https://andtech.co.jp/business-consulting Inquiries regarding this matter ────────────── AndTech Co., Ltd. PR Manager Aoki Email address: pr●andtech.co.jp (Please change ● to @ and contact us) All program items below (please take a look if you are interested in details) ────────────────────────────
∽∽────────────────────────∽∽ Part 1 Nanoimprint application to optical waveguides for AR/VR (overview and application to tilted diffraction gratings) *Currently, the lecturer is devising the latest lecture program. We will update this page as soon as it is completed. ∽∽────────────────────────∽∽ Part 2 Application of imprint technology to semiconductor packaging [Purpose of the lecture] As we enter the era of IoT, various semiconductors and sensors are being mounted on a variety of substrates. Under these circumstances, by lowering the mounting temperature of semiconductor chips, it becomes possible to expand various applications. On the other hand, we will discuss the impact that the ever-increasing degree of integration of semiconductor chips has on packaging, and explain attempts to respond to increased pin counts and narrower pitches using imprint technology.
Specifically, as a method for forming wiring and bumps on
semiconductor packaging boards, imprint technology is used to create fine, high-aspect wiring and bumps that are difficult to achieve with conventional printing methods, faithful to the design pattern size and with smooth edge shapes. Explain that it is possible to form [Program] 1. Semiconductor implementation in the IoT era 1.1 Diversifying semiconductor chips, sensors, and substrates 1.2 Lower temperature of flip-chip bonding process 1.3 Application example 2. Semiconductor chip technology trends 2.1 Semiconductor chip pin count trend 2.2 Pad pitch trend of semiconductor chips 2.3 System-in-package (SiP) integration trends 3. Application of imprint technology to
semiconductor packaging 3.1 Why imprint technology? 3.2 Wiring and bump formation process flow using imprint technology 3.3 Simultaneous formation of 10μm pitch wiring and bumps using hard replica 3.4 Wiring formation on board wiring step using soft replica 4. Summary and future outlook [Q&A] [Key points of the lecture] Various printing methods have been studied to form wiring and bumps at low
temperatures. This method, which uses imprint technology, makes it possible to form fine, high-aspect wiring and bumps with smooth edges, which are difficult to achieve with printing methods.
∽∽────────────────────────∽∽ Part 3 Development of nanoimprint lithography technology and application to semiconductor
microfabrication [Purpose of the lecture] Currently, we are exploring the potential of nanoimprinting, but some problems have arisen regarding its application. First is the issue of reducing the gap between shots, second is the issue of alignment marks, and finally is the issue of template processing accuracy. In this overview, we will explain what kind of negative effects these problems have on device application, and propose and discuss countermeasures. [Program] Challenges in applying nanoimprint devices [Q&A] *Product and service names mentioned in this news release are trademarks or registered trademarks of each company. *The information contained in this news release is current as of the date of announcement. It is subject to change without prior notice. Above