[CMC Research] [New Publication Announcement] Everything About Semiconductor Packaging and Assembly Technology – Learn from the Basics to the Cutting Edge: Semiconductor Post-Processing and Chiplet Technology – Author: Yosuke Hirumuta : CMC Research, Inc.
CMC Research Press Release: September 10, 2025 [New Book Announcement] Everything About Semiconductor Packaging and Assembly Technology – Learn from the Basics to the Cutting Edge: Semiconductor Post-Processing and Chiplet Technology – Author: Yosuke Hirumuta : CMC Research, Inc. ★Covers everything from the basics of semiconductor post-processing to the latest chiplet technology. Includes explanations of failure cases and analysis methods, condensing practical knowledge directly relevant to research and development and implementation!
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automobiles, and they have now evolved into core components that hold the key to economic security. Meanwhile, while cutting-edge
semiconductor manufacturing processes are pushing the limits of miniaturization and entering a new dimension of 2nm, the vast majority of semiconductors do not require this cutting-edge technology. However, the continued advancement of device performance is driving the industry toward “chiplet” technology, which integrates multiple chips. In light of this trend, this book focuses on the “back-end” of semiconductor manufacturing—semiconductor packaging—and provides a thorough explanation from the basics to advanced applications. In the past, semiconductor packages were merely “containers” that protected chips and connected them to the outside world. However, in response to modern demands, packages have evolved toward higher pin counts, higher functionality, and smaller size, evolving from DIP to QFP and then BGA, resulting in the creation of a wide variety of packages. This book explores the history of packaging evolution and development while delving deeply into the technologies and key points of each
manufacturing process. One of the unique features of this book is its comprehensive presentation of the author’s valuable experience and knowledge gained over many years in semiconductor manufacturing. Tales of development struggles, failures, and lessons learned offer practical insights that cannot be gained through theory alone. Specific examples of defects such as chip cracks, wire breaks, and popcorn cracks, as well as explanations of evaluation and analysis methods during prototyping and development, will be of great use to engineers and researchers in the semiconductor industry. In addition, to provide a comprehensive understanding of the latest technological trends, chapters are devoted to explaining efforts to comply with environmental regulations such as RoHS and PFAS, as well as 2.5D/3D packaging and chiplet technology, which will likely influence the future direction of semiconductor packaging. We hope that this book will serve as a compass, deepening knowledge and helping pave the way for the future for young engineers involved in the semiconductor industry, students aiming to enter this field, and all those who wish to systematically learn about semiconductor packaging. Yosuke Himuta ������ Author Yosuke Hirumuta Hirumuta Engineer Office
Quality/Technology Consultant Professional Engineer (Mechanical Department/Processing/Production Systems/Industrial Machinery) [Career] 1984-2003: Fujitsu Ltd. 2003～2009：Spansion Japan Co., Ltd. 2009-2022: NV Devices Co., Ltd. (formerly Fujitsu Devices Co., Ltd.) 2022.11-present: Independent Professional Engineer [Achievements] – Kawauchi Polytechnic Junior College, Kyushu Polytechnic College (Part-time Lecturer) – Kagoshima Hybrid Rocket Research Group (Team KROX) Rocket Development Project, sponsored by the Katanoda
Laboratory, Department of Mechanical Engineering, Graduate School of Science and Engineering, Kagoshima University: Currently Participating – Spot consultations related to semiconductor post-processing: Many – Manufacturing quality improvement, reliability enhancement: Many consultations – Processing projects for silicon wafers and other industrial applications: Currently participating 【Areas of Expertise】 Semiconductor post-processing and assembly, quality and reliability fields [Research History] ・Development of high-end packaging technology for supercomputers, etc. ・All areas of LF packaging technology for memory and logic devices ・Development of MCP packaging for mobile devices and improvement of mounting connection reliability ・Development of sensor devices and SiP (System in Package) for special applications ・Etc. 【Affiliated Academic Societies】 Japan Institute of Professional Engineers, Japan Institute of Electronics Packaging ������ Book Proofreading and Table of Contents Overview Part I: Fundamentals of Post-Processing, Assembly, and Design in Semiconductor Manufacturing 1. Introduction 2. Semiconductor Packaging Basics: The Evolution and Development of Packages 2.1 SIP and DIP were the Beginnings, but Package Forms Diversified with the Advancement of Printed Circuit Board Technology 2.1.1 The History of Package Evolution 2.1.1.1 Early Developments 2.1.1.2 Technological Evolution 2.1.1.3 Contemporary Trends 2.1.1.4 Future Outlook 2.1.2 Unit Systems 2.2 THD (Through-Hole Device) and SMD (Surface-Mount Device) 2.2.1 Various Packages 2.2.2 THD (Through-Hole Device) 2.2.2.1 SIP (Single Inline Package) and DIP (Dual Inline Package) 2.2.2.2 PGA (Pin Grid Array) and LGA (Land Grid Array) 2.2.3 SMD (Surface Mount Device) 2.2.3.1 SOJ (Small Outline J-leaded package) 2.2.3.2 SON (Small Outline Non-leaded) and QFN (Quad Flat Non-leaded) 2.2.3.3 SOP (Small Outline Package) 2.2.3.4 TSOP (Thin Small Outline Package) 2.2.3.5 QFJ (Quad Flat J-leaded) 2.2.3.6 QFP (Quad Flat Package) 2.2.3.7 BGA (Ball Grid Array) 2.2.3.8 WLP (Wafer Level Package) 2.2.3.9 TCP (Tape Carrier Package) 2.2.4 Fleeting Packages (Representative Packages) 2.2.4.1 QIP (Quad Inline Package) 2.2.4.2 LCC (Leadless Chip Carrier) 2.2.4.3 SVP (Small Vertical Package or Surface Vertical Package) 2.2.4.4 BCC (Bump Chip Carrier) 2.2.4.5 CSOP (C-leaded Small Outline Package) 2.3 Ceramic Packages, Plastic (Lead Frame) Packages, and Printed Circuit Board Packages 2.3.1 Ceramic Package 2.3.2 Lead Frame Package 2.3.2.1 Typical Lead Frame Manufacturing Methods 2.3.2.2 Stamping (Press) 2.3.2.3 Etching 2.3.3 Printed Circuit Board Package 3. Packaging Process (Typical Examples) 3.1 Packaging Process for Ceramic Packages 3.2 Packaging Process for Plastic (Lead Frame) Packages 3.3 Packaging Process for Printed Circuit Board Packages 4. Technologies and Key Points of Each Manufacturing Process 4.1 Pre-Packaging Process 4.1.1 BG (Back Grinding Process) and Dicing Process 4.1.2 DB (Die Bond) 4.1.2.1 AuSi eutectic bonding 4.1.2.2 Adhesive (Ag paste) 4.1.2.3 DAF (Die Attach Film) 4.1.3 WB (Wire Bond) 4.1.3.1 Wedge Bonding 4.1.3.2 Ball Bonding 4.1.3.3 Wire Material 4.2 Encapsulation and Molding Process 4.2.1 Seam Weld (Encapsulation: Ceramic Package) 4.2.2 Mold Encapsulation 4.2.2.1 Transfer Molding 4.2.2.2 Multi-Plunger Molding 4.2.2.3 Compression Molding 4.3 Post-Assembly Processes 4.3.1 Exterior Plating 4.3.1.1 Sn Plating, Sn-Bi Plating 4.3.2 Cutting and Shaping 4.3.3 Ball Attachment 4.3.4 Singulation 4.3.5 Stamping 4.4 Bump and Flip Chip Package Assembly Process 4.4.1 Rewiring and Wafer Bumping 4.4.2 FC (Flip Chip) 4.4.2.1 C4 (Controlled Collapse Chip Connection) 4.4.2.2 C2 (abbreviation for Chip Connection) 4.4.2.3 ACP/ACF 4.4.2.4 NCP/NCF 4.4.3 Underfill (UF) 4.5 Tape Carrier Package (TCP) Assembly Process 4.5.1 Bump (Plated Bump) 4.5.2 Inner Lead Bonding (ILB) 5. Testing Process and Key Points 5.1 Typical Testing Process 5.2 BI (Burn-in) Process 5.3 Visual Inspection (Lead Scan) Process 5.4 Packaging Process and Key Points 5.4.1 Baking and Moisture Absorption Control 5.4.2 Tray Packaging 5.4.3 Taping Packaging 6. Examples of assembly and mounting-related defects experienced in the past 6.1 Chip crack 6.2 Wire breakage 6.3 Package swelling or cracking 6.3.1 Popcorn cracks 6.3.2 Surface blistering/peeling 6.4 Package peels off from board after mounting 6.5 BGA balls come off (fall off or break) 6.6 Package burns (burns) 7. Examples of Evaluation and Analysis Methods During Prototyping and Development 7.1 Destructive Testing and Strength Verification 7.2 MSL (Moisture Absorption and Reflow Test) 7.3 Mechanical Testing and Temperature Cycle Testing 7.4 SAT (ultrasonic testing), XRAY (CT), and shadow moire 7.5 Unpacking, polishing, and inspection 7.6 Guidelines from JEITA and JEDEC 8. RoHS and green compliant 8.1 Lead-free compliant 8.2 Improved flame retardant resin 8.3 PFAS/PFOS/PFOA-free 9. Future 2.5D/3D Packages and Chiplet Technologies 9.1 Advanced Packaging Strategy 9.2 Chiplet Technology 9.2.1 CoWoS(R)️ 9.2.2 Backside Power Supply 9.3 Hybrid Bonding 9.4 The Key to Manufacturing is the Bonding Between the Chip and the Interposer and the TSV 9.4.1 3D Packaging Challenges 9.4.2 Chip-to-Chip Bonding Methods 9.4.3 Interposer Materials 9.4.4 Who is responsible for ensuring the reliability of the stacked chips? 9.5 Optical Chiplet Packaging Technology (Photonic-Electronic Integrated Devices) 9.6 Chiplet Design Rules 9.7 Evolution of Substrates and Interposers Will Determine the Future 9.7.1 Glass Core Substrate 10. At the end Reference/cited literature list Part II Integration of existing chips using chiplet technology: Advantages, disadvantages, and technical issues 1. Benefits 1.1 Reduction of development period and cost 1.1.1 Shortening design period 1.1.2 Reducing development costs 1.1.3 Responding to high-mix, low-volume production 1.1.4 Risk reduction and yield improvement 1.1.5 Heterogeneous integration and optimal process node selection 1.1.6 Integration of different semiconductor materials 1.1.7 Parts procurement flexibility 2. Disadvantages 2.1 Increase in packaging costs 2.2 Performance and power efficiency issues 2.2.1 Performance degradation due to interconnect 2.2.2 Decrease in power efficiency 2.2.3 Complexity of thermal management 2.2.4 Supply chain complexity and management challenges 2.2.5 Ensuring interoperability 2.2.6 New challenges in design and verification 2.2.7 Quality Assurance 2.3 技術的課題 2.3.1 インターコネクト技術の高度化 2.3.2 高密度接続技術 2.3.3 Evolution and improvement of thermal management technology 2.3.4 Thermal stress relaxation 2.3.5 Precision packaging technology and yield improvement 2.3.6 Establishment of testing/verification methods/traceability 2.4 Developing a design ecosystem 2.4.1 Chiplet library and design tools 3. Conclusion References Part III About PFAS in semiconductor back-end processes 1. Impact on the semiconductor industry and development of alternative materials 2. Regarding semiconductor post-processing 3. Regulations if there is a conflict 3.1 EU REACH Regulation
(Regulations on Registration, Evaluation, Authorization and
Restriction of Chemical Substances) 3.2 EU POPs Regulation (Regulation on Persistent Organic Pollutants) 3.3 Japan’s Chemical Substances Control Law (Law Concerning the Examination of Chemical Substances and Regulation of Manufacturing, etc.) 3.4 Regulations in other countries
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Nishikicho, Chiyoda-ku: https://cmcre.com/ ) provides cutting-edge technology and market information. We hold seminars and publish books on market trends and technology trends for various materials and chemicals. ������ 関連情報 1.Related books “World’s Chiplets/Advanced Packaging Latest Industry Report Chiplet/Advanced Packaging” ■ From: November 13, 2024 ■ Fixed price: Main unit (booklet version) 140,000 yen (154,000 yen including tax) Base CD (PDF version) 190,000 yen (209,000 yen including tax) ★ E-mail newsletter members: 10% off the list price! ■ Size: A4 size, paperback, 200 pages ■ Edited and published by: CMC Research Co., Ltd. ISBN 978-4-910581-60-6
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